The present invention relates to a test on a semiconductor integrated circuit and, more particularly, to a test which can be conducted on a large scale semiconductor integrated circuit without using a high-performance tester body having a memory for a large capacity.
A test on an ordinary semiconductor integrated circuit (IC) is carried out as follows. Continuous digital signals (input pattern) at the H (High) or L (Low) level are supplied from the tester body of a semiconductor tester to a device to be tested. It is then determined whether or not continuous digital signals at the H or L level (output pattern) as expected in correspondence with the level of the input signals are outputted from the device.
FIG. 5 shows an example of a conventional test system for a semiconductor integrated circuit. A tester body 501 is a semiconductor testing apparatus and supplies continuous digital signals at either the H or L level (input pattern) via a signal line 504 to a device 503 to be tested (which is a semiconductor integrated circuit) and placed on a test board 502. The tester body 501 receives continuous digital signals at either the H or L level (output pattern) output by the device 503 in correspondence with the input signals. The tester body 501 then determines whether or not the signals are as they are expected to be.
A memory for storing the input and output patterns used for testing the device to be tested is provided in the tester body 501.
Since the scale and packing density of the present day semiconductor integrated circuits (device 503 to be tested) is increasing, the number of input and output patterns used for tests is also increasing. Accordingly, it is becoming difficult day by day to carry out a test using a cheap tester body 501 having only a limited memory capacity.
Especially, in the case of carrying out a test by using a long serial pattern typified by a scan system, it is necessary to store not only data of a signal line which changes but also data of a signal line which does not change. A very large memory capacity or an optional function dedicated to a serial test is therefore necessary.
It is the object of the present invention to provide a testing method capable of performing a test using a long serial pattern typified by a scan method using a cheap tester body having a limited memory capacity without requiring an optional function dedicated to a serial test.
A tester according to one aspect of this invention comprises a first storage which stores an input signal for testing a device to be tested; a second storage which stores an expectation value signal output when the device normally operates in response to the input signal; and a comparator which compares the expectation value signal from the second storage with an actual output signal from the device. The first storage, the second storage, and the comparator are provided on a test board.
Further, the first and second storages are non-volatile memories. The tester further comprises a first high-speed storage for reading the input signal for test from the first storage and transmitting the read input signal to the device; and a second high-speed storage for reading the expectation value signal from the second storage and transmitting the read signal to the comparator.
A test system according to another aspect of this invention comprises a first storage which stores an input signal for testing a device to be tested; and a second storage which stores an expectation value signal which is output when the device normally operates in response to the input signal. A memory in the device is used for temporarily storing both the input signal for test from the first storage and the expectation value signal from the second storage. The expectation value signal is compared with an actual output signal from the device.
Further, the tester and test system further comprises a first level-varying unit capable of varying the level of an input signal to the device; and a second level-varying unit capable of varying a threshold level of an output signal from the device.
A method of testing a semiconductor integrated circuit according to still another aspect of this invention comprises the steps of storing an input signal for testing a device to be tested into a first storage; storing an expectation value signal which is output when the device normally operates in response to the input signal into a second storage; inputting the input signal for testing from the first storage into the device; and comparing an output signal output from the device with the expectation value signal from the second storage.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.